ELECTRONIC DESIGN PROCESSES (EDP) 2008 – CALL FOR PAPERS

APRIL 17-18^th, 2008

 

MONTEREY BEACH HOTEL, MONTEREY, CALIFORNIA

 

The Electronic Design Processes (EDP) Workshop provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. The workshop focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves. Please visit http://www.eda.org/edps to see the list of past EDP Workshop speakers and presentations:  2007, 2006, 2005, 2004, 2003, 2002, 2001, 2000.

Here is a printable version of this CFP: http://www.eda.org/edps/edp08/edp08-cfp.pdf

            

EDP 2008 is over; we hope to see you next year!

The workshop was successful, with many interesting talks and a lot of discussion. Richard Goering of SCDSource noted "Of these, EDP is probably the least familiar to engineering audiences – and it's by far the smallest in terms of attendance. But if you want to hear about the latest in design automation technology in an interactive, informal setting, it's the place to be. This year's EDP workshop had a strong focus on the challenges of multicore development and programming, and two articles below cover some insightful and provocative sessions on that topic."

 

PRESS COVERAGE of EDP 2008

• SCDSource - Speaker: Let's get 'manycore' parallel programming right
• SCDSource - Case study reveals challenges of multicore programming
• EDN/Steve Leibson - Can We Please do it Right This Time?
• EDN/Steve Leibson - The Last Few MHz
• Chip Design Magazine/Taken for Granted - Let's reach a consensus

 

THEMES IN 2008:  Portable Devices, Design for Manufacturing

We solicit papers and proposals for special/panel sessions that shed light on the methodologies used for real current and future chip and system designs. Topics include but are not limited to:

         • Methodology for the rapid design of embedded/portable systems

         • Best practices and experiences with Power or DFM Methodology focus 

         • Multi-voltage Design and Power Management, Power Analysis 

         • Restrictive Design Rules (RDR) Impact on DFM 

         • Process/Device Characterization, Modeling implications 

         • Standards Activity: Helping or Hurting? 

         • Status of EDA Industry

         • Multi-Core Programming/Implications 

         • Flow Integration, Scaling, and Migration

         • Human Issues: Large & Distributed Teams, Off-shoring, Training and Education

• Key Trends: Future Methodology Needs, Impact of Design Manufacturing Interface, Interoperability, Impact of Web, Licensing Models, and Platform

 

PAPER SUBMISSION 

Authors should submit full-length, original and unpublished papers (maximum 20 pages in single-column double spaced format, or 6 pages in double-column conference proceedings format) along with author contact information. Proposals for special and panel sessions may also be submitted; a 1-page description along with organizer contact information is required. Send Proposals via email to: edps@eda.org

 

IMPORTANT DATES

Submission Deadline: 29 February 2008       Acceptance Notification: 17 March 2008

Camera Ready Copy: 31 March 2007             On-site Registration: 16 April 2007

 

EDPS 2008 Workshop Program:

Speaker	Affiliation	Title/Area of Talk
Thursday, April 17, 2008
08:30 AM - 09:10 AM Welcome, Continental Breakfast Host: Patrick H. Madden, SUNY Binghamton
Keynote Address - 9:10am - 9:50am Timothy G. Mattson / Intel Parallel Computing: Can We Please Do it Right?
Session:  Embedded Microprocessor Design 10:00am - 12:30 Session Chair: TBD
Grant Martin, Steve Leibson	Tensilica	Embedded Boot Camp: AMP vs. SMP
Radhika Thekkath	MIPS	Max Out Your Multi's
Ian Rickards	ARM	Myths of Multicore
Ray Brinks	Sonics Inc.	Microprocessor Centric SoC's are Dead
Akash Deshpande	ARC	Solutions for SoC Design
Lunch: 12:30 - 1:15 Lunch Discussion: Parallel Computing Bingo
Session:  EDA Standards Panel 1:15 - 2:45pm Session Chair and Organizer: John Darringer (IBM)
John Darringer	IBM	Panel Overview
Gary Delp, Technical Director	SPIRIT	The Spirit View
Jake Buurma	SI2	Creating Effective EDA Standards
Victor Berman, Chairman	IEEE DASC	IP Challenges
Rohit Kapur, Chairman	IEEE TTSC	Creating Standards in TTTC
Session:  Manufacturing Challenges and Solutions 3pm - 4:15pm Session Organizer: TBD
Puneet Gupta	UCLA/Blaze	The Electrical Design-Manufacturing Interface
Andres Torres	Mentor Graphics	Regular Designs and Computational Lithography: Their Past, Present, and Future
Anantha Sethuraman	DFMSim	After the Hype, Are We Ready To Do DFM?
Session: Nuts and Bolts of EDA Tools 4:30pm - 5:45pm Session Chair: TBD
Patrick Groeneveld	Magma	TCL as an EDA tool flow integrator: the good, the bad, and the ugly.
Joao Geada	CLKda	Efficient Use of Multicore Processors for Timing Analysis
Igor Markov	U Michigan	On Libraries, Reuse, and the Value of EDA Software
EDP Banquet Dinner Panel Discussion on EDA and the Industry Press Richard Goering, SCDsource Gabe Moretti, GabeOnEDA Steve Leibson, EDN
Friday, April 18, 2008 8:30am-9am Continental Breakfast
Session:  EDA Venture Capital Outlook 9am - 10:30
Juan-Antonio Carballo	Argon VC	An Updated Venture Capital Outlook
Renu Raman	Tallwood VC	Semiconductor Trends and Investments
Daya Nadamuni	Gary Smith EDA	The Forecast for EDA
Session:  Power Aware Verfication 10:45-11:30
Bhanu Kapoor, Auturo Salz, Shankar Hemmady	Mimasic/Synopsys	Multi-Voltage Power Managment Verification Issues
Srivasta Vasudevan	Synopsys	Verification Minimization with Karnaugh Maps
Lunch Talk: Aman Joshi, Director of IC Tools, Sun Microsystems Multicore Design: OpenSparc T1 and T2 11:45-1pm
Session: Take Me To A Higher Level - Virtualization, ESL, and the Next Generation of EDA Tools 1:15pm - 3pm
Larry Lapides	Imperas	Open Virtual Platforms
Michel Genard	Virtutech	Virtualized Software Development
Rajesh Gupta	UC San Diego	The Next EDP Challenge: Cost of ASIC Design & Validation
Rishiyur Nikil	Bluespec	Using Parallel Atomic Transactions in SoC Design
Alec Stanculescu	Fintronic	FinSimMath: An Extension of Verilog for Mathematical Descriptions
Closing Remarks

 

Organizing Committee:

General Chair:  Patrick H. Madden

Technical Program Chair:  Gary Smith

Steering Committee Chair: Bhanu Kapoor

Publicity Chair:  Steve Grout

 

Program Committtee:

Michael Bohm (AccelChip)              Aparna Dey (Cadence)                  John Lillis (UIC)

Takahide Inoue (STARC)                  Andrew B. Kahng (UCSD)              José Augusto Lima (U. of Minho)                               

Gabe Moretti (Gabe on EDA)             Naresh Sehgal (Intel)                    Kumar Venkatramani (SoftJin)

Sandeep Shukla (Virginia Tech)     Gary Smith (GarySmithEDA)          Bill Halpin (Synplicity)

Bhanu Kapoor (Mimasic)                  Patrick Madden (Binghamton)      Igor Markov (U. of Michigan)

Elaheh Bozorgzadeh (UCI)                Juan-Antonio Carballo (Argon)    Matt Gutthaus (UCSC)

Steve Grout (Consultant)                 Dwight Hill (Synopsys)                   Patrick Groeneveld (Magma)