The release Fixed and Floating point packages were designed to run under VHDL-2006.   The problem with that is the many people want to run them under VHDL-93, and use them in current synthesis and simulation projects.   The purpose of this page is to allow users to use these packages NOW.   This page is organized by tool, so you will see entries for each tool, a ZIP file with the necessary code (modified from the original source) for this tool, and a note on how it is to be used.   For simulation tools, all of the code is included in the ZIP file. For synthesis tools, only the synthesizable packages are included.

The floating point packages were designed to be 100% IEEE 754 compatible.   For synthesis, this just isn't practical.   I recommend that you that you go into the top of "float_pkg" and change the constants as follows:

    constant float_exponent_width : NATURAL    := 8;
    constant float_fraction_width : NATURAL    := 15;  -- 16 bits of precision
    constant float_round_style    : round_type := round_zero; -- disable rounding
    constant float_denormalize    : BOOLEAN    := false; -- no denormal numbers
    constant float_check_error    : BOOLEAN    := false; -- NO NAN and overflow checks
    constant float_guard_bits     : NATURAL    := 0; -- no guard bits
In your source code, you should use this type:
  begin
    signal float1 : float (float_exponent_width downto -float_fraction_width);

If you are an EDA vendor, and would like to test your tool against these packages, please download the "modelsim.zip" (which has the fewest changes in it) and try it aginst your syntheis/simulation tool. If you have any issues please drop me an e-mail.

The NEXT step is a Verilog package. Interested?