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Viewing Issues (1 - 50 / 1577) [ Print Reports ]  [ CSV Export ] [ First Prev 1 2 3 4 5 6 7 8 9 10 11 ... Next Last ]
    PIDTypeCategorySeverityStatusUpdatedSummary
  0003195Errata[SystemVerilog P1800]
SV-AC		majornew2010-09-02Local Variables Flow Out Issue in and/or/intersect/implies
   0001185Enhancement[SystemVerilog P1800]
SV-BC		featurenew2010-09-02user defined functions on instantiations
   0003188Enhancement[SystemVerilog P1800]
SV-CC		minorassigned (Chuck_Berking)2010-09-01No way to distinguish join, join_none, and join_any for fork-join blocks in VPI
   0003176Errata[VIP]
BCL		minorresolved (Janick Bergeron)2010-09-01uvm_report_global_server does not implement singleton properly
   0002571Clarification[SystemVerilog P1800]
SV-AC		minorresolved (Scott Little)2010-09-01confusing assertion clock inference rule
  0002205Clarification[SystemVerilog P1800]
SV-AC		minorresolved (Erik_Seligman)2010-09-01$asseroff, $assertkill and $asserton description is ambiguous
   0003194Clarification[Power Aware P1801]
6.40 set_isolation		minornew2010-09-01Clarification on the term 'sibling' when used to define location.
   0001477Errata[SystemVerilog P1800]
SV-CC		majorassigned (Chuck_Berking)2010-09-01virtual interfaces information model
   0003192Errata[SystemVerilog P1800]
SV-CC		minorassigned (Chuck_Berking)2010-09-0137.8 section has wrong value definitions for vpiAccessType
   0003193Errata[SystemVerilog P1800]
SV-CC		minorassigned (Chuck_Berking)2010-09-01Need defined value for built-in class type process-class for vpiClassType property.
   0002845Errata[SystemVerilog P1800]
SV-EC		majornew2010-09-01virtual interface type checking versus interface type that had been defparam'ed
   0003179Errata[VIP]
BCL		crashassigned (Edgar Jimenez)2010-08-31compilation crash with OVM and UVM libraries are included
   0003175Enhancement[VIP]
BCL		majorassigned (John Fowler)2010-08-31Need a means to control message emission that is based on more than purely 'verbosity'.
   0002751Enhancement[SystemVerilog P1800]
SV-AC		majorassigned (Ben Cohen)2010-08-31P1800-2009: checker formal arguments may not be connected to interfaces // WHY?
   0002476Errata[SystemVerilog P1800]
SV-AC		minorassigned (Erik_Seligman)2010-08-31Need clarification about system functions $onehot, etc
  0003166Errata[Power Aware P1801]
6.42 set_level_shifter		majorassigned (John_Biggs)2010-08-31FAQ: Level shifter & isolation strategy on macro pins
   0002770Errata[Power Aware P1801]
6.24 create_supply_set		minorassigned (Gary_Delp)2010-08-31How are functions for supply set handles created?
  0003165Clarification[Power Aware P1801]
6.40 set_isolation		minorassigned (Qi Wang)2010-08-31FAQ: How to avoid implementation tools insert duplicated isolation (or level-shifter cells)
   0003182Errata[Power Aware P1801]
7 Queries		minorassigned (Rick Koster)2010-08-31Dealing with wired logic
   0003191Enhancement[SystemVerilog P1800]
SV-AC		minornew2010-08-31Allow sequence methods with sequence expressions
   0001706Errata[SystemVerilog P1800]
SV-EC		majornew2010-08-30Meaning of static prefix for virtual interface assignments
  0002080Clarification[SystemVerilog P1800]
SV-EC		majorresolved (Dave Rich)2010-08-30"::" is ambiguous in parameterized classes
  0002022Errata[SystemVerilog P1800]
SV-EC		minorresolved (Dave Rich)2010-08-30index value width extension for associative arrays
  0002018Clarification[SystemVerilog P1800]
SV-EC		majorresolved (shalom)2010-08-30Is a queue an array or not?
  0001740Errata[SystemVerilog P1800]
SV-EC		minorresolved (shalom)2010-08-30Item 1457 did not correct section 10.5.3
  0001672Errata[SystemVerilog P1800]
SV-EC		textresolved (shalom)2010-08-3018.9: "type" should be "option"
  0000802Clarification[SystemVerilog P1800]
SV-EC		featureresolved (shalom)2010-08-30Assigning too many elements to a queue
  0000251Enhancement[SystemVerilog P1800]
SV-EC		minorresolved (Dave Rich)2010-08-30multiple user defined bins for cross
   0002451Clarification[SystemVerilog P1800]
SV-EC		majorresolved (Steven Sharp)2010-08-30Omitting body defaults
   0001349Errata[SystemVerilog P1800]
SV-EC		featureresolved (Steven Sharp)2010-08-30fork/join_none: what if parent thread terminates without blocking statement?
   0002794Clarification[SystemVerilog P1800]
SV-EC		minorresolved (Jonathan Bromley)2010-08-30Clarify queue methods return status
   0002956Errata[SystemVerilog P1800]
SV-EC		textresolved (Steven Sharp)2010-08-30clarify class 'process' definition (9.7 vs 18.13.3, 18.13.4, 18.13.5)
   0002950Errata[SystemVerilog P1800]
SV-EC		majorresolved2010-08-30virtual method prototype matching
  0002949Errata[SystemVerilog P1800]
SV-EC		minorresolved (Jonathan Bromley)2010-08-30LRM is silent about the semantics of referencing a clocking block output
   0003190Errata[UCIS]
API		minornew2010-08-30Be inclusive with language type definition enum
   0003116Errata[SystemVerilog P1800]
SV-CC		minornew2010-08-30No method/transition path to get to typespecs of named events or named event arrays
   0003115Errata[SystemVerilog P1800]
SV-CC		minornew2010-08-30Clarification needed on lifetime semantics of DPI import formals when called reentrantly
  0002107Errata[SystemVerilog P1800]
SV-BC		minorassigned (Dave Rich)2010-08-30Clarifications needed for scope operator
  0002108Clarification[SystemVerilog P1800]
SV-BC		minorassigned (Dave Rich)2010-08-30Clarifications needed for importing of scope names
  0002734Enhancement[SystemVerilog P1800]
SV-BC		minorresolved (shalom)2010-08-29Mechanism to initialize an array to a constant value
  0002574Errata[SystemVerilog P1800]
SV-BC		majorresolved (shalom)2010-08-29class_scope parameter identifier missing in ps_parameter_identifier
  0002533Clarification[SystemVerilog P1800]
SV-BC		minorresolved (shalom)2010-08-29Equivalent to what?
  0002525Enhancement[SystemVerilog P1800]
SV-BC		featureresolved (shalom)2010-08-29Allow hierarchical references in $unit scope
  0001685Clarification[SystemVerilog P1800]
SV-BC		minorresolved (shalom)2010-08-296.3.2 should be clarified as allowing string literals
  0001223Enhancement[SystemVerilog P1800]
SV-BC		minorresolved (shalom)2010-08-29red hyperlinked BNF?
  0001222Clarification[SystemVerilog P1800]
SV-BC		featureresolved (shalom)2010-08-29clarify explicitly whether a module may instantiate itself
  0001204Enhancement[SystemVerilog P1800]
SV-BC		featureresolved (shalom)2010-08-29Add lists of figures, tables, syntaxes
  0001162Errata[SystemVerilog P1800]
SV-BC		minorresolved (shalom)2010-08-29A.1.4: list_of_port_declarations BNF rule
  0001029Errata[SystemVerilog P1800]
SV-BC		minorresolved (shalom)2010-08-29some 1364 examples use 1800 keywords
  0000991Errata[SystemVerilog P1800]
SV-BC		textresolved (shalom)2010-08-292, 12: improving syntax boxes
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