RE: Requirements list and agenda


Subject: RE: Requirements list and agenda
From: Erich Marschner (erichm@cadence.com)
Date: Thu Aug 01 2002 - 08:18:34 PDT


Tom,

Your spreadsheet does not include any entries from the FVTC requirements summary. Was that intentional?

Erich

-------------------------------------------
Erich Marschner, Cadence Design Systems
Senior Architect, Advanced Verification
Phone: +1 410 750 6995 Email: erichm@cadence.com
Vmail: +1 410 872 4369 Email: erichm@comcast.net

| -----Original Message-----
| From: Tom Fitzpatrick [mailto:fitz@co-design.com]
| Sent: Thursday, August 01, 2002 10:53 AM
| To: sv-ac@eda.org
| Subject: Requirements list and agenda
|
|
| Hi Gang,
|
| I've attached an Excel spreadsheet with the requirements
| that have been
| submitted, grouped into preliminary categories. I'd like to
| try to discuss
| these at today's meeting. Here's the agenda I propose:
|
| Agenda:
| I. Attendance
| II. Email Reflector Update
| III. Requirements Review/Approval Process
| IV. Requirements List Review
| A. Questions/Clarifications
| B. Additions/Corrections
| V. Other Issues
| A. Cindy's List
| B. Resolution Process
| VI. Next Meeting
|
| Call-in info
| 405-244-5555 x4615
| 9am-11am PDT, 12pm-2pm EDT
|
| Thanks,
| -Tom
| ------------------------------------------------------
| Tom Fitzpatrick
| Director of Technical Marketing
| Co-Design Automation, Inc.
| ------------------------------------------------------
| Email: fitz@co-design.com Mobile: (978)337-7641
| Tel: (978)448-8797 Fax: (561)594-3946
| Web: www.co-design.com
| www.superlog.org
| ------------------------------------------------------
| SUPERLOG = Faster, Smarter Verilog
| ------------------------------------------------------
|



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