Accellera SV-AC Technical Committee

SystemVerilog Assertion Committee

The SV-AC is the subcommittee of the Accellera SystemVerilog Technical Committee tasked with defining an assertion language extension to the Verilog language. This assertion language section is included as part of the SystemVerilog standard being developed with other Accellera SV sub-committees.

The first draft of the assertion extension was included in the SystemVerilog 3.0 release. This was extended and is now an enhanced stanard in SV v3.1. This version is now being examined, enhanced, corrected, and extended and will be included in the SystemVerilog v3.1a release.

Chair: Faisal Haqaue, Cisco
Co-Chair: Steve Meier, Synopsys
Full Committee Membership Listing

System Verilog Links

System Verilog SV-AC v3.1a Operating Guidelines
System Verilog v3.1 final standard specification
SV-AC Future Enhancements List (Post SV3.1)
SV-AC Mail Reflector (sv-ac@eda.org)
SV-AC Mail Reflector Archives

Links

Old Assertion Committee Mail Reflector Archives

Accellera OVL TC Web Page
Accellera OVL TC Mail Reflector Archives
OVL Home Page

Meeting Schedule and Minutes

Every other Monday 9AM, next meeting September 8 Domestic: 888-635-9997 International: 763-315-6815 Participant: 959066# Meeting Logistics:

SV-AC Documentation

SystemVerilog 3.0 Specification (see Section 11 for Assertions)

Working document Rev0.79 for Assertions

Collection of Assertion Requirements

Assertion Requirements List versions 3.1a-Rev1.6 8/25/03

Assertion Requirements List versions 3.0

Assertion Requirements List versions 0.1 [html] [xls format]