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| ID | Category | Severity | Date Submitted | Last Update | |||
| 0001198 | [SystemVerilog P1800] V-1364 | feature | 2005-12-09 16:53 | 2007-09-10 17:46 | |||
| Reporter | Cliff Cummings | View Status | public | ||||
| Assigned To | shalom | ||||||
| Priority | immediate | Resolution | fixed | ||||
| Status | closed | Product Version | |||||
| Summary | 0001198: Support a container to define how to interface to a set of signals. | ||||||
| Description |
There should be a place that one can define an interface and then from there modules can use the interface without having to duplicate the information. This information would include: List of signals in the interface. Assertions defining correct behavior of interface. Functional coverage points observing complete usage of the interface. Named (sub)set of signals with port directions so a module can define how it uses the interface. |
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| Additional Information |
Was issue 475 in 1364 database - Adam Krolnik http://www.boydtechinc.com/btf/report/full_pr/475.html [^] |
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| Tags | No tags attached. | ||||||
| Type | Enhancement | ||||||
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