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| ID | Category | Severity | Date Submitted | Last Update | |||
| 0001200 | [SystemVerilog P1800] V-1364 | feature | 2005-12-09 17:06 | 2008-01-07 05:09 | |||
| Reporter | Cliff Cummings | View Status | public | ||||
| Assigned To | shalom | ||||||
| Priority | immediate | Resolution | fixed | ||||
| Status | closed | Product Version | |||||
| Summary | 0001200: Provide an assertion statement with the capability to use industry standard property specification. | ||||||
| Description |
There needs to be a way to allow verilog writers to easily express their intent on how their code should work. An assertion should be supported to allow expression of a property that must be satisfied, or never satisfied. The property form should be an industry standard form so that the assertion/property can be used in simulation, synthesis, code coverage, model checking, etc. There need to be three kinds of statements: assertion - a property that requires verification coverage - to record the occurrence of the property success. assumptions - to define artificial restrictions, and requirements necessary to complete a proof. |
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| Additional Information |
Was issue 477 in 1364 database - Adam Krolnik http://www.boydtechinc.com/btf/report/full_pr/477.html [^] |
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| Tags | No tags attached. | ||||||
| Type | Enhancement | ||||||
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