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| ID | Category | Severity | Date Submitted | Last Update | |||
| 0001497 | [SystemVerilog P1800] SV-BC | text | 2006-06-05 05:58 | 2008-01-09 04:27 | |||
| Reporter | shalom | View Status | public | ||||
| Assigned To | shalom | ||||||
| Priority | immediate | Resolution | fixed | ||||
| Status | closed | Product Version | |||||
| Summary | 0001497: delete mention of macromodules | ||||||
| Description |
1364-2005 deleted mention of macromodules, except in BNF of module_keyword, in the keyword list, and in 1364 12.1, which says, "The keyword macromodule can be used interchangeably with the keyword module to define a module. An implementation may choose to treat module definitions beginning with the macromodule keyword differently." This is documented in http://www.boyd.com/1364_btf/report/full_pr/425.html. [^] The reasons for deleting their mention are: - Most importantly, if you list them with modules only in some places and not in others, it gives the impression that in the other places, there may indeed be a difference. Otherwise, why are they not mentioned everywhere? - On the other hand, if they are not listed anywhere, except for that sentence in 1364 12.1, it strengthens the impression that they are the same. - If they are indeed interchangeable, there is no need to mention them, and their use should not be encouraged. - If they are not interchangeable (e.g., Verilog-XL treats them specially), then they are not portable, and again their use should not be encouraged. - They make the LRM more verbose. - They make the code more verbose. Unfortunately, the 1800 LRM mentions them no less than 17 times, which is 13 too many. Let's delete the 13 unneeded mentions. |
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| Tags | No tags attached. | ||||||
| Type | Errata | ||||||
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