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| ID | Category | Severity | Date Submitted | Last Update | |||
| 0001644 | [SystemVerilog P1800] V-1364 | text | 2006-10-23 05:11 | 2007-09-13 13:36 | |||
| Reporter | shalom | View Status | public | ||||
| Assigned To | shalom | ||||||
| Priority | immediate | Resolution | no change required | ||||
| Status | closed | Product Version | |||||
| Summary | 0001644: 12.3.5: bad indentation | ||||||
| Description |
Geoffrey Coram reports: In the example in 12.3.5: module topmod; wire [4:0] v; wire a,b,c,w; modB b1 (v[0], v[3], w, v[4]); endmodule module modB (wa, wb, c, d); inout wa, wb; input c, d; tranif1 g1 (wa, wb, cinvert); not #(2, 6) n1 (cinvert, int); and #(6, 5) g2 (int, c, d); endmodule the first 'endmodule' and the following 'module modB' should not be indented. |
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| Additional Information | |||||||
| Tags | No tags attached. | ||||||
| Type | Errata | ||||||
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