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ID |
Category |
Severity |
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Date Submitted |
Last Update |
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0001708 |
[SystemVerilog P1800] SV-BC |
feature |
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2007-01-05 13:54 |
2008-05-08 21:48 |
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Reporter |
Brad Pierce |
View Status |
public |
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Assigned To |
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Priority |
normal |
Resolution |
open |
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Status |
new |
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Product Version |
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Summary |
0001708: $period check should support max and output, not just min and input |
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Description |
Patrick Phung (patrick.phung@xilinx.com) writes --
I have an enhancement request for the SDF standard and the Verilog standard.
The existing $period check supports the minimum period check on input port only.
I would like to request a minimum period check and a maximum period check for both input port and output port.
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Additional Information |
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| Tags |
No tags attached. |
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Type |
Enhancement |
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Attached Files |
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