Subject: Re: Call for vote on P1164 change proposals
From: Stephen Bailey (Stephen.Bailey@synopsys.com)
Date: Fri Jan 31 2003 - 18:31:47 PST
> CP-001 Uncomment xnor operators
Accept
> CP-002 Add shift operators for vector types
Accept
> CP-003 Add array/scalar logical operators
Reject.
In general, the analysis/recommendation is fine. However, I prefer that the
range of the result be consistent with 1076. My reason being that if the
design/designer typically uses N downto 0 ranges, then the result would be
consistent with what is typical of the design/designer (assuming that the vector
operand is typical). Also, I believe some tools already do it this way (even
though it isn't standard).
But, I think this is a relatively minor detail since the result is usually
assigned to something else and then has the range of the target. (Which means
that failing to persuade the WG to change, I wouldn't vote No on the ballot
because of this.)
> CP-004 Add capacitive drive strength
Accept
> CP-005 Make vector result subtypes same as 1076 operators
Reject. (see comments for CP-003 above)
> CP-006 Add logical reduction operations/operators
Reject.
I think we need the unary reduction operands. I think they should be added to
1076 first and then overloaded here. I see no benefit in typing "xor_reduce"
instead of xor. Nor do I see a benefit in later having overloadable unary
reduction operators in the language and then not overload them in 1164.
My recommendation is that this group request the 200x group to quickly agree to
adding the unary reduction operators so 1164 and 1076.3 can exploit them
immediately. This would be a good test as to how quickly we can move things on
the 200x side of things. (I think having a short list of relatively
straight-forward fast lane items is worth considering in 1076 200x.)
> CP-009 Provide 'image attribute
Accept.
I agree with the analysis and recommendation.
If this issue is as "hot" as unary reduction, then let's also add this to the
200x "fast lane" issues.
> CP-010 Add match functions like numeric_std.std_match
Accept.
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Stephen Bailey
Staff Corporate Applications Engineer, VHDL Simulation
Synopsys Inc.
sbailey@synopsys.com
303-775-1655 (voice/mobile)
650-584-4893 (corporate voice mail)
Read Verification Avenue:
http://www.synopsys.com/va
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